1. Field of the Invention
This invention generally relates to non-volatile memories and fabrication methods thereof, and more particularly, to a non-volatile memory having an ONO (Oxide Nitride Oxide) film and a fabrication method thereof.
2. Description of the Related Art
In recent years, development of non-volatile memories on which data is rewritable has been widespread. In the technical field of such non-volatile memories, development has been striving to downsize the memory cells and increase the memory capacity.
Floating-gate flash memories, non-volatile memories on which the charge is stored in the floating gate, are widely used. However, as the memory cell is downsized for high storage density, it becomes more difficult to design floating-gate flash memories because, as the memory cell of the floating-gate flash memory is downsized, the tunnel oxide film must necessarily be thinner. This is because thinner tunnel oxide film increases the leakage current flowing across the tunnel oxide film. In addition, there arises a reliability problem wherein the charge stored in the floating gate is discharged by a defect introduced into the tunnel oxide film.
To address the above-mentioned problems, there are flash memories that have an ONO (Oxide/Nitride/Oxide) film such as MONOS (Metal Oxide Nitride Oxide Silicon) type or SONOS (Silicon Oxide Nitride Oxide Silicon) type films. These are flash memories where the charge is stored in a silicon nitride film, called a trap layer, sandwiched between layers of the silicon oxide films. In this type of flash memory, the charge is stored in a silicon nitride film which is serving as an insulation film. Accordingly, even if there is a defect in the tunnel oxide film the trap layer is not discharged, unlike the floating-gate flash memory. Also, multi-level bits can be stored in the trap layer of one memory cell, advantageously increasing the storage capacity of the non-volatile memory.
FIGS. 1A through 1D describe a flash memory having a conventional ONO film and the fabrication method thereof (hereinafter, referred to as the conventional fabrication technique). FIGS. 1A through 1D are cross-sectional views of conventional flash memories which includes memory cells and peripheral circuit regions. A memory cell region is shown on the left side and a peripheral circuit region is shown on the right side.
In FIG. 1A, there is provided a p-type silicon semiconductor substrate 100. On the silicon substrate 100, there is provided a first silicon oxide layer 110 to serve as a tunnel oxide film, a silicon nitride layer 112 to serve as the trap layer, and another silicon oxide layer 114 to serve as a protection film for implantation. A photoresist 120 is then applied and, by using general photolithographic techniques, openings 140 are created in regions for forming the bit lines and forming source/drain regions in the memory cell region. Here, a reference numeral L11 denotes the width of the opening 140.
Next, referring to FIG. 1B, arsenic (As) ions, for example, are implanted into the bit line and the source/drain regions and thermal treatment is implemented to form an N-type low-resistance layer 150 for the bit line and the source/drain regions. Here, a reference numeral L12 denotes the width of the low-resistance layer 150. A channel region 156 corresponds to a region between a pair of source/drain regions 150.
Then, referring to FIG. 1C, the silicon oxide layer 114, which is a protection film, is removed and a second silicon oxide layer 116 is formed.
Next, referring to FIG. 1D, the second silicon oxide layer 116, the silicon nitride layer 112, and the first silicon oxide layer 110 provided in the peripheral circuit region are removed. Then, another silicon oxide layer 170, to serve as the gate oxide film, is formed in the region forming the peripheral circuit. In addition, there is provided a gate metal 182 in the peripheral circuit, a control gate in the memory cell, and a polysilicon layer in the memory cell region to serve as a word line 180. Subsequently, the memory cells and the peripheral circuit are fabricated in accordance with commonly used fabrication methods and, thus, flash memory having an ONO film is completed.
Also, in order to reduce the resistance value of the bit line, Japanese Patent Application Publication No. 2002-170891 (hereinafter, referred to as Patent Document 1) discloses a flash memory having an ONO film in which a silicided metal layer is included in a portion of the bit line.
In the conventional fabrication technique, it was difficult to downsize the low-resistance layer 150, which is the bit line as well as the source/drain region having the size of L12. The size L12 is greater than the size L11 of the opening 140 by an amount of lateral diffusion due to the ion implantation. The size L11 of the opening 140 has limitations up to approximately half the wavelength of a photolithography machine. For example, if a commonly used KrF photolithography machine is employed, it is difficult to make the size L11 equal to or narrower than 100 nm. Accordingly, it is also difficult to make the size L12 equal to or narrower than 100 nm. As the size L12 of the low-resistance layer 150 of the bit line and the source/drain region is downsized, the resistance of the bit line is increased, causing a problem of degrading the program and erase characteristics.
To address the aforementioned problem, as described in Patent Document 1, there is a conventional technique of forming the first low-resistance layer and the second low-resistance layer. The first low-resistance layer is formed by implanting ions into the bit line and the second low-resistance layer of low-resistance silicided metal film is thereafter formed partially on the first low-resistance layer. However, with the technique disclosed in Patent Document 1, the second low-resistance layer cannot successively be formed in a current flowing direction, therefore not sufficiently lowering the resistance of the bit line. In addition, the silicided metal film is provided between the sidewall control gates. Thus, unless the width of the bit line is increased, the silicided metal film cannot be formed on the low-resistance layer. This conventional technique is therefore not compatible with the demand for downsizing. Furthermore, unless there are provided two polysilicon layers, the memory cell cannot be completed. Since, generally, the gate in the peripheral circuit region is formed with a single layer of polysilicon film, the structure having two layers of polysilicon films in the memory cell causes the fabrication process of the peripheral circuit to become quite complicated.
On the other hand, in the conventional fabrication technique, it is difficult to further deposit a low-resistance layer on the bit line region 150, because the photoresist is used as the mask. At least 200° C. is necessary for forming the low-resistance layer, in general, and such temperatures exceed a glass-transition temperature of the photoresist.